16.3 State machines: Mealy and Moore models

State machines are the backbone of sequential logic circuits. They model systems with finite states, where outputs depend on both current inputs and previous states. This unit dives into two key models: Mealy and Moore machines.

Mealy and Moore machines differ in how they generate outputs. Mealy machines use both current state and input, while Moore machines rely solely on the current state. Understanding these models is crucial for designing efficient sequential circuits.

State Machine Models

Finite State Machines and Sequential Circuits

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• Finite state machine (FSM) models the behavior of a system with a finite number of states
• FSMs are used to design and analyze sequential circuits that have memory and whose outputs depend on both the current inputs and the previous state
• Synchronous sequential circuits are a type of FSM where state transitions occur on the rising or falling edge of a clock signal, ensuring that the circuit operates in a predictable and synchronized manner

Mealy and Moore Machines

• Mealy machine is an FSM where the output depends on both the current state and the current input
  • In a Mealy machine, the output logic is a function of the current state and the current input (output = f(state, input))
  • Mealy machines can produce different outputs for the same state, depending on the input (more output combinations)
• Moore machine is an FSM where the output depends only on the current state
  • In a Moore machine, the output logic is a function of only the current state (output = f(state))
  • Moore machines produce the same output for a given state, regardless of the input (simpler output logic)

State Representation

State Diagrams and Tables

• State diagram is a graphical representation of an FSM that shows the states, transitions between states, and the conditions for each transition
  • States are represented by circles or rectangles, and transitions are represented by arrows connecting the states
  • Transition conditions (inputs) and outputs are labeled on the arrows or next to the states (Mealy or Moore)
• State table is a tabular representation of an FSM that lists all possible combinations of current state, input, next state, and output
  • Rows represent the current state and input combinations, while columns represent the next state and output
  • State tables provide a compact and organized way to describe the behavior of an FSM

State Registers and Encoding

• State register is a set of flip-flops that stores the current state of the FSM
  • The number of flip-flops in the state register depends on the number of states in the FSM (n flip-flops can represent 2^n states)
  • Common state encoding techniques include binary, one-hot, and gray coding, each with their own advantages and trade-offs (e.g., binary encoding is compact but may have more complex next state logic)

State Machine Components

Next State and Output Logic

• Next state logic determines the next state of the FSM based on the current state and input
  • Combinational logic circuits (e.g., gates, multiplexers) are used to implement the next state logic based on the state transition conditions
  • The outputs of the next state logic are connected to the inputs of the state register to update the state on the next clock cycle
• Output logic generates the outputs of the FSM based on the current state (Moore) or the current state and input (Mealy)
  • Combinational logic circuits are used to implement the output logic based on the state (and input) values
  • The outputs of the output logic can be connected directly to external pins or to other internal circuits

State Transitions and Timing

• Transition is the change from one state to another based on the current state and input conditions
  • Transitions occur on the rising or falling edge of the clock signal in synchronous sequential circuits
  • The next state logic and state register work together to ensure that the FSM transitions to the correct next state
• Timing considerations are crucial in the design of FSMs to ensure proper operation and avoid issues such as setup and hold time violations or race conditions
  • The clock period must be long enough to allow the next state and output logic to settle before the next rising or falling edge of the clock
  • Techniques such as pipelining and retiming can be used to optimize the timing and performance of FSMs in complex designs