2.2 Instruction set architecture and addressing modes

Instruction set architecture and addressing modes are key concepts in microcontroller design. They define how processors execute commands and access data. Understanding these elements is crucial for writing efficient assembly code and optimizing microcontroller performance.

RISC and CISC architectures offer different approaches to instruction design. Addressing modes determine how operands are accessed. These concepts shape how we program and interact with microcontrollers, influencing their speed and efficiency in embedded systems.

Instruction Set Architecture

RISC and CISC Architectures

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• Reduced Instruction Set Computing (RISC) architectures focus on a simplified instruction set with fixed-length instructions and a large number of registers
  • Aim to execute instructions in a single clock cycle (ARM processors)
• Complex Instruction Set Computing (CISC) architectures have a more complex instruction set with variable-length instructions and fewer registers
  • Instructions may take multiple clock cycles to execute (x86 processors)
• RISC architectures tend to have better performance due to faster instruction execution and simpler hardware design
• CISC architectures offer more complex instructions, reducing the number of instructions needed for a given task

Instruction Types and Opcodes

• Instructions are the basic commands that a processor can execute, consisting of an opcode and operands
• Opcode (operation code) specifies the operation to be performed by the processor
  • Examples of opcodes include ADD, SUB, MOV, JMP
• Operands are the data or memory locations on which the instruction operates
  • Can be registers, memory addresses, or immediate values
• Common instruction types include arithmetic (addition, subtraction), logical (AND, OR, XOR), data transfer (move, load, store), and control flow (jump, branch, call)

Instruction Encoding and Operands

• Instructions are encoded as binary values, with the opcode and operands occupying specific bits within the instruction
• The number and type of operands depend on the instruction and the architecture
  • Some instructions may have no operands (NOP), while others may have one (INC), two (ADD), or more operands
• Operands can be specified using various addressing modes, which determine how the processor interprets the operand value
• The size of the operands (8-bit, 16-bit, 32-bit, 64-bit) depends on the architecture and the specific instruction

Addressing Modes

Immediate and Direct Addressing

• Immediate addressing uses a constant value as the operand, which is directly encoded in the instruction
  • Example:

    MOV R1, #10

    moves the value 10 into register R1
• Direct addressing uses the memory address of the operand as part of the instruction
  • The address is directly specified in the instruction
  • Example:

    MOV R2, [0x1000]

    moves the value stored at memory address 0x1000 into register R2

Indirect and Indexed Addressing

• Indirect addressing uses a register that contains the memory address of the operand
  • The register holds a pointer to the memory location where the operand is stored
  • Example:

    MOV R3, [R1]

    moves the value stored at the memory address pointed to by register R1 into register R3
• Indexed addressing combines a base address with an offset or index to calculate the effective address of the operand
  • The base address is typically stored in a register, and the offset can be an immediate value or stored in another register
  • Example:

    MOV R4, [R2 + 4]

    moves the value stored at the memory address calculated by adding 4 to the value in register R2 into register R4

Register Addressing

• Register addressing uses registers to store both the operands and the result of an instruction
• The operands are directly specified as registers in the instruction
  • Example:

    ADD R1, R2, R3

    adds the values in registers R2 and R3 and stores the result in register R1
• Register addressing is the fastest addressing mode since no memory access is required
• The number of available registers varies between architectures, with RISC architectures typically having more registers than CISC architectures