5.3 Main memory organization and technologies

Main memory is the heart of a computer's memory system. It stores data and instructions currently in use by the processor. This section explores how main memory is organized, addressing schemes, and the key differences between volatile and non-volatile memory types.

We'll dive into various memory technologies like SRAM, DRAM, and ROM. We'll also look at techniques to improve memory performance, such as interleaving and error handling. Understanding these concepts is crucial for optimizing computer system design and performance.

Main Memory Organization

Memory Structure and Addressing

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• Main memory, also known as primary memory or Random Access Memory (RAM), is a critical component of a computer system that stores data and instructions currently in use by the processor
• Main memory is organized into a linear array of cells, each with a unique address, allowing the processor to access any memory location directly in a random access manner
• Memory cells are typically organized into rows and columns, forming a matrix-like structure, with each cell storing a fixed number of bits (usually 8 bits or 1 byte)
• The capacity of main memory is measured in bytes, with common sizes ranging from gigabytes (GB) to terabytes (TB) in modern systems (16GB, 32GB, 64GB)

Memory Volatility and Communication

• Main memory is volatile, meaning that it retains data only when power is supplied to the system
  • When the power is turned off or the system is restarted, the contents of main memory are lost
  • This is in contrast to non-volatile memory, such as hard disk drives or solid-state drives, which retain data even without power
• The processor communicates with main memory through the memory controller, which manages the flow of data between the processor and memory
  • The memory controller translates memory addresses generated by the processor into physical addresses in memory
  • It also handles tasks such as memory refresh, error detection, and correction, and memory access scheduling

Memory Technologies

Static Random Access Memory (SRAM)

• Static Random Access Memory (SRAM) is a type of main memory that uses bistable latching circuitry to store each bit, allowing for faster access times compared to DRAM
  • SRAM is more expensive and has lower storage density than DRAM, limiting its use in large main memory capacities
  • SRAM is often used for small, high-speed memory caches within the processor, such as the Level 1 (L1) and Level 2 (L2) caches, due to its fast access times (1-2 clock cycles)
• SRAM cells consist of six transistors (6T) arranged in a cross-coupled inverter configuration, forming a bistable latch that can store one bit of data
  • The bistable nature of SRAM cells allows them to retain data as long as power is supplied, without the need for periodic refresh
  • The six-transistor design of SRAM cells makes them larger and more expensive compared to DRAM cells, which typically use only one transistor and one capacitor per bit

Dynamic Random Access Memory (DRAM)

• Dynamic Random Access Memory (DRAM) is the most common type of main memory in modern computer systems
  • DRAM stores each bit of data using a capacitor and a transistor, which requires periodic refreshing to maintain the stored data
  • DRAM is cheaper and has higher storage density compared to SRAM, making it suitable for large main memory capacities (4GB, 8GB, 16GB)
• DRAM cells consist of a transistor and a capacitor, where the presence or absence of charge in the capacitor represents a binary 1 or 0, respectively
  • The capacitor in a DRAM cell gradually loses its charge over time due to leakage currents, requiring periodic refresh operations to restore the stored data
  • The simple structure of DRAM cells allows for higher storage density and lower cost compared to SRAM, but at the expense of slower access times and the need for refresh
• Common types of DRAM include Synchronous DRAM (SDRAM), Double Data Rate (DDR) SDRAM, and Graphics DDR (GDDR) SDRAM
  • SDRAM synchronizes its operations with the system clock, enabling faster and more efficient data transfer compared to asynchronous DRAM
  • DDR SDRAM transfers data on both the rising and falling edges of the clock signal, effectively doubling the data rate compared to standard SDRAM (DDR3, DDR4, DDR5)
  • GDDR SDRAM is a specialized type of DRAM designed for graphics processing units (GPUs), offering higher bandwidth and lower latency compared to standard DDR SDRAM

Read-Only Memory (ROM)

• Read-Only Memory (ROM) is a type of non-volatile memory that stores permanent data and instructions that are not meant to be modified during normal operation
  • ROM retains its contents even when the power is turned off, making it suitable for storing critical system information and boot instructions
  • Examples of data stored in ROM include the system's firmware, BIOS (Basic Input/Output System), and bootloaders
• Various types of ROM include Mask ROM, Programmable ROM (PROM), Erasable Programmable ROM (EPROM), and Electrically Erasable Programmable ROM (EEPROM)
  • Mask ROM is programmed during the manufacturing process and cannot be modified later, making it suitable for large-scale production of fixed firmware or software
  • PROM can be programmed once by the user using a special device called a PROM programmer, allowing for custom firmware or software
  • EPROM can be erased by exposing it to ultraviolet light and then reprogrammed, providing flexibility for firmware updates or modifications
  • EEPROM can be erased and reprogrammed electrically, without the need for physical removal or ultraviolet light exposure, making it more convenient for frequent updates

Memory Interleaving and Error Handling

Memory Interleaving

• Memory interleaving is a technique used to improve memory access performance by dividing memory into multiple banks that can be accessed simultaneously
  • Interleaving allows for parallel access to different memory locations, reducing the impact of memory access latency
  • By accessing multiple memory banks concurrently, the overall memory bandwidth is effectively increased
• Common interleaving schemes include two-way, four-way, and eight-way interleaving, depending on the number of memory banks used
  • In two-way interleaving, memory is divided into two banks, with even-addressed locations in one bank and odd-addressed locations in the other
  • Four-way interleaving uses four memory banks, with consecutive memory locations spread across the banks in a round-robin fashion
  • Eight-way interleaving further increases the number of memory banks to eight, allowing for even more parallel access to memory locations
• Memory interleaving can be implemented at various levels, such as cache line interleaving, page interleaving, or bank interleaving
  • Cache line interleaving spreads consecutive cache lines across different memory banks, reducing the impact of cache line conflicts
  • Page interleaving distributes memory pages across different banks, improving the performance of page-based memory accesses
  • Bank interleaving assigns consecutive memory addresses to different banks, enabling parallel access to adjacent memory locations

Error Detection and Correction

• Error detection and correction mechanisms are employed in main memory to ensure data integrity and reliability
  • Memory errors can lead to system crashes, data corruption, or incorrect results, making error handling crucial for system stability
  • Common causes of memory errors include manufacturing defects, cosmic radiation, and electrical interference
• Parity checking is a simple error detection method that adds an extra bit (parity bit) to each byte or word of data stored in memory
  • The parity bit indicates whether the number of 1s in the data is odd (odd parity) or even (even parity)
  • When data is read from memory, the parity is checked to detect any single-bit errors, but parity checking cannot correct errors
• Error Correction Codes (ECC) are more advanced error detection and correction mechanisms that can detect and correct single-bit errors and detect (but not correct) multi-bit errors
  • ECC memory modules have additional memory chips that store the error correction information, which is used to reconstruct the correct data when an error is detected
  • Common ECC schemes include Hamming codes and Single Error Correction, Double Error Detection (SECDED) codes
• Hamming codes add multiple parity bits to the data, allowing for the detection and correction of single-bit errors and the detection of double-bit errors
  • The number and position of the parity bits are determined by the Hamming code algorithm, which ensures that each data bit is covered by multiple parity bits
  • When an error is detected, the Hamming code can identify the location of the erroneous bit and correct it by flipping its value
• SECDED codes extend Hamming codes by adding an additional parity bit, enabling the correction of single-bit errors and the detection of double-bit errors
  • SECDED codes are commonly used in modern ECC memory modules due to their balance between error correction capabilities and memory overhead
  • In case of a single-bit error, SECDED codes can correct the error on the fly, while double-bit errors are detected but not corrected, triggering a system alert or shutdown

Memory Access and Performance

Memory Access Patterns and Locality

• Memory access patterns refer to the way in which a program or algorithm accesses data in memory, which can significantly impact the overall system performance
  • Efficient memory access patterns can take advantage of caching mechanisms and memory hierarchy to reduce the average memory access time
  • Poor memory access patterns can lead to frequent cache misses, increased memory latency, and reduced system performance
• Locality of reference is a key principle in memory access patterns, which states that a program tends to access memory locations that are close to each other (spatial locality) or have been recently accessed (temporal locality)
  • Spatial locality refers to the tendency of a program to access memory locations that are close to each other in the address space
  • Temporal locality refers to the tendency of a program to access the same memory locations repeatedly within a short period of time
• Programs with good locality of reference can benefit from caching mechanisms, as the frequently accessed data can be stored in faster cache memory
  • When a program exhibits strong spatial locality, the cache can prefetch adjacent memory locations, reducing the number of cache misses and memory accesses
  • When a program exhibits strong temporal locality, the recently accessed data can be kept in the cache, allowing for faster subsequent accesses to the same data
• Techniques to improve memory access patterns and locality include:
  • Organizing data structures to maximize spatial locality, such as using arrays instead of linked lists when possible
  • Minimizing the number of pointer-based data structures, which can lead to scattered memory accesses and poor spatial locality
  • Reusing data within loops to take advantage of temporal locality and reduce the number of memory accesses
  • Blocking or tiling algorithms to work on smaller subsets of data that fit in the cache, improving both spatial and temporal locality

Memory Access Latency and Caching

• Memory access latency is the time delay between initiating a memory request and receiving the data from memory, which can be a significant bottleneck in system performance
  • Factors affecting memory access latency include the physical distance between the processor and memory, the memory technology used (e.g., SRAM vs. DRAM), and the memory hierarchy design
  • Memory access latency is typically measured in clock cycles or nanoseconds, with faster memory technologies and shorter distances resulting in lower latencies
• Cache memory is a small, fast memory located close to the processor, designed to bridge the performance gap between the processor and main memory
  • Caches store frequently accessed data and instructions, allowing the processor to access them quickly without the need to fetch them from slower main memory
  • Common cache levels include Level 1 (L1), Level 2 (L2), and Level 3 (L3) caches, with L1 being the smallest and fastest, and L3 being the largest and slowest
• Cache misses occur when the requested data is not found in the cache memory, requiring the processor to fetch the data from slower main memory
  • Cache misses can be classified into compulsory misses (first-time access to a memory location), capacity misses (cache is too small to hold all the required data), and conflict misses (multiple memory locations mapping to the same cache line)
  • Cache misses result in increased memory access latency and reduced system performance, as the processor must wait for the data to be fetched from main memory
• Techniques to mitigate the impact of memory access latency include:
  • Increasing cache sizes and levels to store more frequently accessed data closer to the processor, reducing the number of cache misses
  • Employing prefetching techniques to predict and fetch data from memory before it is actually needed by the processor, hiding the memory access latency
  • Optimizing memory access patterns in software to improve locality of reference and reduce cache misses, as discussed in the previous section
  • Using memory interleaving and parallel memory access schemes to increase memory bandwidth and reduce the impact of latency, as explained in the memory interleaving section