7.2 Interrupt service routines (ISRs)

Interrupt Service Routines (ISRs) are the backbone of interrupt handling in embedded systems. They're automatically called when an interrupt occurs, saving the processor state, performing necessary actions, and restoring the state before returning to the interrupted program.

ISRs must be fast and efficient to minimize latency. They determine the interrupt source, service it, and acknowledge it. Writing reentrant code is crucial to avoid data corruption and ensure smooth execution in multi-interrupt scenarios.

Interrupt Handling

Interrupt Service Routine (ISR) Structure and Execution

• ISR called automatically when an interrupt occurs
• Saves processor state (context) on the stack before executing ISR code
• Performs necessary actions to handle the specific interrupt
• Restores processor state from the stack before returning to the interrupted program
• Must be as short and fast as possible to minimize interrupt latency and avoid delaying other interrupts

Interrupt Handler and Acknowledgment

• Interrupt handler code executed when an interrupt occurs
• Determines the source of the interrupt (reads status registers or interrupt controller)
• Performs necessary actions to service the interrupt (reading/writing data, updating variables, etc.)
• Acknowledges the interrupt to the device that generated it
  • Clears the interrupt flag or writes to a specific register
  • Allows the device to generate new interrupts

Reentrant Code Considerations

• Reentrant code can be safely executed by multiple interrupt handlers simultaneously
• Avoids using shared resources (global variables, hardware registers) without proper synchronization
• Uses local variables and parameters for temporary storage
• Prevents corruption of shared data structures
• Ensures deterministic behavior and avoids race conditions

Context Management

Context Saving during Interrupt Handling

• Processor state (context) automatically saved on the stack when an interrupt occurs
  • Includes program counter (PC), status register, general-purpose registers
• Ensures the interrupted program can resume execution correctly after the ISR completes
• Allows the ISR to use processor registers without affecting the interrupted program
• Context saving performed by hardware or software depending on the processor architecture

Context Restoration after Interrupt Handling

• Processor state (context) restored from the stack before returning from the ISR
• Ensures the interrupted program resumes execution from the point where it was interrupted
• Restores the values of program counter (PC), status register, general-purpose registers
• Context restoration performed by hardware or software depending on the processor architecture

Interrupt Configuration

Interrupt Vector Table Setup and Usage

• Interrupt vector table contains the addresses of ISRs for each interrupt source
• Each interrupt source assigned a unique interrupt number or identifier
• Processor uses the interrupt number as an index into the vector table to find the corresponding ISR address
• ISR addresses stored in the vector table during system initialization
  • Typically done by the startup code or operating system
• Vector table located at a specific memory address (e.g., the beginning of the memory space)

Configuring Interrupt Priorities and Enabling/Disabling Interrupts

• Interrupt priorities determine the order in which simultaneous interrupts are handled
  • Higher priority interrupts preempt lower priority ones
• Priorities assigned to each interrupt source using special registers or configuration bits
• Interrupts can be globally or individually enabled/disabled using control registers
  • Allows selective servicing of interrupts based on system requirements
• Proper configuration of priorities and enabling/disabling interrupts ensures critical tasks are handled promptly and less critical ones are postponed if necessary